1. Field of the Invention
The present invention relates to a transmission method for a serial periphery interface (SPI) serial flash, and more particularly, to a transmission method for a double data rate (DDR) serial periphery interface (SPI) serial flash.
2. Description of the Related Art
A parallel flash generally uses many pins (e.g., above 20 pins) for data input or data output, to receive power, to receive addresses and for receiving control signals. However, some of the pins are not used during operation. Using the parallel flash in a printed circuit board (PCB) or the like usually results in some issues including a large area occupied on a PCB, higher cost of the system, and more complicated control circuit. To facilitate the board design and reduce the cost, a serial flash has been developed.
FIG. 1 shows the pin assignment of an SPI serial flash 10. Compared with the parallel flash, the SPI serial flash 10 has much fewer pins. Each pin function is given briefly as follows. Pin SCK, serial clock, provides the timing of the serial interface (i.e., SPI). Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. Pin SI, serial data input, transfers commands, addresses, or data serially into the SPI serial flash 10. The inputs are latched on the rising edge of the serial clock. Pin SO, serial data output, transfers data serially out of the SPI serial flash 10. Data is shifted out on the falling edge of the serial clock. Pin CE#, chip enable, enables the SPI serial flash 10 by a high to low transition thereon, and it must remain low for the duration of any command sequence. WP#, write protect, is used to enable or disable a bit to activate or de-activate the program operation. Pin HOLD#, hold, temporarily stops serial communication with the SPI serial flash 10 without resetting the SPI serial flash 10. VDD is a power supply voltage. VSS is a ground voltage.
FIG. 2 shows a known read sequence of the SPI serial flash 10. A signal CE#, chip enable, must remain active low for the duration of the read sequence. A read instruction is initiated by executing an eight-bit command (e.g., 03H), followed by 24 address bits that are indicated by three ADDs. The read command (03H) received through Pin SI takes eight periods of SCK, from period 0 to period 7. The output of the data in the 24 address bits begins on the falling edge of the 31st period of SCK until the signal CE# switches from low to high, in which each byte (eight bits) of the data takes eight periods of SCK. Pin SO remains high impedance before the output of the data. Normally, the SPI serial flash has a data output rate of 50 MHz, i.e., 50M bits/second, which is lower than the data output rate of a parallel flash. The SPI serial flash 10 with only one output pin obtains a compact board design at the expense of the data output rate. For the SPI serial flash 10, one bit of data is inputted through Pin SI in one clock period of SCK. Also, the clock rate of SCK limits the inputs of commands, addresses and data, and limits the output rates of the read data.
Another approach to improve the data output rate of the SPI serial flash is proposed, which can access data at clock rates up to 75 MHz, compared to other SPI serials flashes that typically operate from 25 MHz to 50 MHz. To double the data output rate, the input pin (i.e., Pin SI, serial data input) of the SPI serial flash is used as another output pin during the output of the data; therefore, two bits can be accessed during one clock period while keeping the same four-pin SPI interface. However, only the data output rate is doubled in this approach and all other operations are still limited by the clock rate.